rai o RA0086A 80 ch segment/common driver for dot matrix lcd specification simplify version 1.1 december 29, 2009 ra i o technology inc. ?copyright raio technology inc. 2009 ?? rai o technology inc. 1/6 www.raio.com.tw
version 1.1 80ch common / segment driver for dot matrix lcd RA0086A 1. introduction the RA0086A is an 80 channels lcd driver lsi which is fabricated by low power cmos high voltage process technology. it can be used either as a commo n driver or as a segment driver, by connecting its cs input to vdd or vss. in segm ent driver mode, it can be interfaced in 1-bit serial or 4-bit parallel method by the controller. in common driver mode, dual type mode is applicable. and in segment mode application, the power down functi on reduces power consumption. 2. features ? power supply voltage: + 5v 10 %, + 3v 10% ? supply voltage for display: 6 to 30v (v dd - v ee ) ? in 80-segment driver or 80-common driver selection, to set cs-pin voltage is vss or vdd ? 4-bit parallel / 1-bit serial data processing (in segment mode) ? single mode / dual mode operation (in common mode) ? power down function (in segment mode) ? applicable lcd duty: 1/64 ? 1/256 ? interface drivers com(cascade) seg(cascade) RA0086A RA0086A ? high voltage cmos process ? available package type: lqfp-100 pin, die 3. block diagram parts number package RA0086A die RA0086Al3n lqfp-100 pin v0 v12 v43 v5 sc78 sc79 sc80 vee m disp0ffb 80-bit 4-level driver 80-bit driver 80-bitdata latch/common data bi-direction shift register 20 x 4-bit segment data bi-direction shift register output level selector power down function data latch control clock control cl1 cl2 cs ams lck sck sc1 sc2 sc3 elb d2-dl d3-dm d4-dr erb vdd vss erb vdd vss d1-sid ?? rai o technology inc. 2/6 www.raio.com.tw
version 1.1 80ch common / segment driver for dot matrix lcd RA0086A 4. signal description 4-1 block description name function com / seg clock control generates latch clock (lck), shift clock (sck) and control clock timing according to the input of cl1, c l2 and control inputs (cs, ams). in common driver application mode, this block generates the shift clock (lck) for the common data bi-directional shift register. com / seg data latch control determines the direction of segm ent data shift, and input data of each bi-directional shift register. in 4-bi t segment data parallel transfer mode, data is shifted by a 4-bit unit. in co mmon driver application mode, data is transferred to the common data shift regi ster directly, which disables this block. seg power down function controls the clock enable state of t he current driver according to the input value of enable pin (elb or erb). if enable input value is ? low ? , every clock of the current driver is enabled and the clock control block works. but if enable input is ? high ? , current driver is disabled and the input data value has no effect on the output level. so power consumption can be lowered. seg output level selector controls the output voltage level acco rding to the input control pin (m and dispoffb). com / seg 20x4-bit segment data bi-directional shift register stores output data value by shifting the input values. in 1-bit serial interface mode application, all 80 sh ift clocks (sck) are needed to store all the display data. but in 4-bit parallel transfer mode application, only 20 clocks are needed. in common driver application mode, this block does not work. seg 80-bit data latch / common data bi-directional shift register in segment driver application mode, the data from the 20x4-bit segment data shift register are latched for s egment driver output. in single-type common driver application,1-bit input dat a (from dl or dr pin) is shifted and latched by the direction according to the shl signal input. in dual- type common application mode, 80-bi t registers are divided by two blocks and controlled independently. com / seg 80-bit level shifter voltage level shifter block for high voltage part. the inputs of this block are of logical voltage level and the outputs of this block are at high voltage level value. these values are input in to the driver. seg 80-bit 4-level driver selects the output voltage level according to m and latched data value. if the data value is "high" the driver output is at selected voltage level (v0 or v5), and in the reverse case t he driver output value is at the non- selected level (v12 or v43). in segment driver application mode, non- selected output value is v2 or v3. and when in common driver application, this value becomes v1 or v4. seg ?? rai o technology inc. 3/6 www.raio.com.tw
version 1.1 80ch common / segment driver for dot matrix lcd RA0086A 4-2 pin description pin i/o name description function interface vdd logical "high" input port (+5v 10%, +3v 10%) vss 0v (gnd) vee p power supply logical "low" for high voltage part power v0, v12, v43, v5 i lcd driver output voltage level bias supply voltage input to drive the lcd. bias voltage divided by the resistance is usually used as a supply voltage source. power sc1 - sc80 o lcd driver output display data output pin which corresponds to the respective latch contents. one of v0, v12, v34 and v5 is selected as a display driving voltage source according to the combination of the latched data level and m signal. lcd cl2 i data shift clock clock pulse input for the bi-directional shift register. ? in segment driver application mode, the data is shifted to 20 x 4-bit segment data shift. the clock pulse, which was input when the enable bit (elb/erb) is in not active condition, is invalid. ? in common driver application mode, the data is shifted to 80-bit common data bi-directional shift register by the cl1 clock.hence, this clock pin is not used (open or connect this pin to vdd). controller m i ac signal for lcd driver output alternate signal input pin for lcd driving. normal frame inversion signal is input in to this pin. controller cl1 i data latch clock ? in segment driver application mode, this signal is used for latching the shift register contents at the falling edge of this clock pulse. cl1 pulse "high" level initializes power- down function block. ? in common driver application mode, cl1 is used as a shifting clock of common output data. controller dispoffb i display off control control input pin to fix the driver output (sc1~sc80) to v0 level,during "low" value input. lcd becomes non-selected by v0 level output from ever y output of segment drivers and every output of common drivers. controller cs i com / seg mode control when cs = "low", RA0086A is used as an 80-bit segment driver. when cs = "high", RA0086A is set to an 80-bit common driver vdd/ vss ams i application mode select according to the input value of the ams and the cs pin, application mode of RA0086A is differs as shown below. cs ams application mode com /seg 0 0 4-bit parallel interface mode. 0 1 1-bit serial interface mode. seg 1 0 single type application mode 1 1 dual type application mode com vdd/ vss ?? rai o technology inc. 4/6 www.raio.com.tw
version 1.1 80ch common / segment driver for dot matrix lcd RA0086A d1_sid, d2_dl, d3_dm, d4_dr. i/o display data input / serial input data / left,right data input output - in segment driver applicati on mode, these pins are used as 4-bit data input pin (when 4-bit parallel interface mode : ams = "low"), or d1_sid is used as serial data input pin and other pins are not used (connect these to vdd) (when 1-bit serial interface mode : ams = "high"). ? in common driver application mode, the data is shifted from d2_dl(d4_dr) to d4_dr(d2_dl), when in single type interface mode (ams = "low"). in dual type application case, the data are shifted from d2_dl and d3_dm (d4_dr and d3_dm) to d4_dr(d2_dl). in each case the direction of the data shift and the connection of data pins are determined by shl input. controller shl i shift direction control when shl = "low", data is shifted from left to right. when shl = "high", the direction is reversed. vdd/ vss elb,erb i/o enable data input/output ? in segment driver application mode, the internal operation is enabled only when enable input (elb or erb) is ? low ? (power down function). when several drivers are serially connect ed, the enable state of each driver is shifted according to the shl input. connect these pins as below. segment driver shl elb erb l output input h input output - in common driver application mode, power down function is not used. open these pins. 5. system block diagram stn controller ra8822 ra8803 ra8806 ra8835 ra6963 stn controller ra8822 ra8803 ra8806 ra8835 ra6963 stn lcd panel RA0086A RA0086A ?? rai o technology inc. 5/6 www.raio.com.tw
version 1.1 80ch common / segment driver for dot matrix lcd ?? ra o technology inc. 6/6 www.raio.com.tw RA0086A i 6. application information 7. package sc28 sc29 sc30 sc31 sc32 sc33 sc34 sc35 sc36 sc37 sc38 sc39 sc40 sc41 sc42 sc43 sc44 sc45 sc46 sc47 sc48 sc49 sc50 sc51 sc52 sc2 sc1 elb cl1 ams cl2 d1_sid d2_dl d3_dm d4_dr vss shl vdd dispoffb m cs v0 v12 v34 v5 vee erb sc80 sc79 sc78 sc77 sc76 sc75 sc74 sc73 sc72 sc71 sc70 sc69 sc68 sc67 sc66 sc65 sc64 sc63 sc62 sc61 sc60 sc59 sc58 sc57 sc56 sc55 sc54 sc53 sc3 sc4 sc5 sc6 sc7 sc8 sc9 sc10 sc11 sc12 sc13 sc14 sc15 sc16 sc17 sc18 sc19 sc20 sc21 sc22 sc23 sc24 sc25 sc26 sc27 raio tm RA0086Al3n 5 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 90 100 95 09xx-n mxts01 date code (year 2009) pin#1.
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